Phase Interpolator Pll In Simulink Computer Science Essay

Phase Interpolator Pll In Simulink Computer Science Essay Phase Locked Loops (PLLs) is a negative feedback system that matches the output frequency to the input frequency. Many applications utilize PLLs such as: frequency synthesizers, skew cancellation, reference clean-up, and clock-data recovery [1]. For frequency synthesizers, the goal is to generate a clock at a higher speed to that of a slower reference clock. For example, generating a 1 GHz signal from a 100 MHz reference signal. This is a common goal for many optical applications. For example, current work performed by AOSense, a leading research and development company in atomic-level sensing requires clock frequencies well into the hundreds of megahertz and even into the gigahertz range. For this reasons, PLLs, such as the HMC698LP5 from Hittite Microwave are commonly used in their designs. standard pll design A basic PLL consist of four main building blocks; Phase Frequency Detector (PFD), Charge Pump (CP), Low Pass Filter (LPF), and Voltage Controlled Oscillator (VCO). Figure 1 is a block diagram of a basic PLL. http://madfeekree.files.wordpress.com/2010/11/basic-pll-block1.png?w=614 Figure 1. Basic PLL Block Diagram [2] The PFD detects any differences in phase and frequency of the reference and feedback signals and generates an appropriate Up or Down signal. These signals are then passed to the CP, in which, the CP sources current into the loop filter (Up signals) or sinks current from the loop filter (Down signals). The LPF converts the signal into an analog voltage for the VCO, in which the VCO outputs a clock at either a higher faster or slower frequency based on the UP DOWN signals generated by the PD. This process is repeated until the output frequency of the VCO properly matches that of the reference frequency. These blocks were constructed and simulated in MATLAB R2112a Simulink. A. Phase Frequency Detector As previously stated, PFD are devices that measures the difference between the reference and feedback clocks. There are two commonly used phase detectors: linear and binary. A linear phase detectors output is a pulse signal with a varying width. When the feedback signal is severely out of phase with the reference signal, the pulse width is larger compared to when the two signals are close to being similar. In contrast, a binary (bang-bang) phase detectors output is a fixed pulse width. This binary output signifies if the feedback signal arrived early or late compared to the reference signal. In this design, a modified version of a linear phase frequency detector was implemented in Simulink, as depicted in figure 2. This PFD generates a logic high for the UP signal when the feedback signals rising edge arrives ahead of the reference signals rising edge for the length of the difference. Similarly, when the feedback singals rising edge arrives after the reference signals rising edge, a logic high is given for the DOWN signal for the duration of the difference. M:SJSUEE 227ProjectReport PicturesFigure 2 PFD.png Figure 2. Phase Frequency Detector Model Applying a test signal to both the reference and variable (feedback) inputs and adjusting the feedback signal with some delay, demonstrates the proper functionality of the PFD. This is illustrated in figure 3. The plot is as given from the top down: UP, DOWN, Reference, and Variable CLK. The UP and DOWN signals are then fed to the charge pump, which directs the loop filter to increase or decrease in voltage, signifying an increase or decrease of the VCO output signal. But first, a discussion on the charge pump and its modelling is in order. M:SJSUEE 227ProjectReport PicturesFigure 3 PFD Test.pngFigure 3. PFD Test Results B. Charge Pump The charge pump block in figure 1 is designed to convert the UP and DOWN signals into current for the loop filter. When the UP signal is logic high, the charge pump will source current to the loop filter and when the DOWN signal is logic high, the charge pump will since current from the loop filter. A circuit representation of a charge pump is given in figure 4 below. From this representation, several key design challenges are noticed. Such as proper current matching from both I1 and I2, parasitic capacitance from the two current sources, and leakage current into and out of the loop filter. M:SJSUEE 227ProjectReport PicturesFigure 4 CP.png Figure 4. Charge Pump Circuit A Simulink model of a charge pump is given in figure 5. Notice how the DOWN signal is subtracted from the UP signal and then fed into a gain of 0.001. This gain value represents the current of the two current sources. The delay representsrepresents the current of the two current sources. The delay represents the capacitor, Cp, in figure 4. M:SJSUEE 227ProjectReport PicturesFigure 5 CP Block.png Figure 5. Charge Pump Model Simulating the charge pump model should show a slowly increasing value as long as the UP signal is high more often than the DOWN signal. Figure 6 below shows such a scenario as the CP_Out signal slowly ramps up. This signifies that the VCO will speed up to force the reference signal to catch up to the data signal. M:SJSUEE 227ProjectReport PicturesFigure 6 CP Test.png Figure 6. CP Test Results C. Loop Filter A loop filter is an entirely passive component device and consist of two capacitors and a resistors as illustrated in figure 7. The loop filter has two branches, the integral path and the proportional path. The integral path is the C2 branch, while the proportional path is the C1 and R branch. As the name implies, the loop filter filters high frequency noise spurs caused by sampling, but this also adds a pole at 1/RC2 [1]. A resistor in the loop filter provides an isolation phase correction from frequency correction. M:SJSUEE 227ProjectReport PicturesFigure 7 Loop Filter Circuit.png Figure 7. Loop Filter Circuit A simulink model of a loop filter is given in figure 8 below. The input to the loop filter is connected to the output of the charge pump. The purpose of the loop filter is to take a current and convert it into a voltage, called the control voltage of the VCO. M:SJSUEE 227ProjectReport PicturesFigure 8 Loop Filter Block.png Figure 8. Loop Filter Model Simulating the loop filter in Simulink gave the plot in figure 9. Re-examining this figure, there may be a an error in the loop filters output as its a sawtooth waveform. This will be compared to the VCO output plot for proper functionality in the next section. Figure 9. Loop Filter Test Results D. VCO The final block in figure 1 is the VCO block. Theres a slight modification to the VCO block compared to that in figure 1 due to the future use of phase interpolation. Due to this, a phase generator block was required. This phase generator block is given in figure 10. M:SJSUEE 227ProjectReport PicturesFigure 10 Phase Generator Block.png Figure 10. Phase Generator Model The purpose of the phase generator block is to allow various phases for the phase interpolation PLL in the forthcoming section. For this, the signal is limited to 360 degrees and various phases are generated as illustrated in figure 11. This is the final design of the VCO. M:SJSUEE 227ProjectReport PicturesFigure 11 VCO Block.png Figure 11. VCO Model A common VCO has a single output, known here as CLK_0. However, due to the use of phase interpolation in the second half of this PLL design, 3 other phases were generated. Each phase separated by 90 degrees. The feedback to the PDF is derived from CLK_0 signal that is passed through a relay that generates a clock signal from a sinusoidal signal. The final PLL design for the first potion is given in figure 12. M:SJSUEE 227ProjectReport PicturesFigure 12 PLL Block.png Figure 12. PLL Design Phase 1 Testing of the pll Testing of the PLL consisted of a pulse generator at the reference clock input. This signal was set to 50 Hz is mentioned in [3]. Figure 13 is a plot of the VCO output (CLK_0). The plot shows that in the beginning, the VCO is attempting to lock and after about 30 seconds, the system locks onto the frequency. M:SJSUEE 227ProjectReport PicturesFigure 13- PLL Test Results.png Figure 13. PLL Phase 1 Test Results phase interpolator design A. Theory Behind Phase Interpolators Phase Interpolators (PI) is a modified version of a PLL. PIs function by taking a weighted values and multiplying and adding them to two signals shifted in phase at the same frequency. These weighted values are call alpha and beta. Beta equals 1 minus alpha as given in equation (1) (1) Where, B. Binary Phase Detector The phase detector used in the PI loop has been modified to act as a bang-bang phase detector instead of a linear phase detector. A modified version of the bang-bang phase detector [4] was used. This modified bang-bang phase detector is given in figure 13i. M:SJSUEE 227ProjectReport PicturesFigure 13i- BBPD Block.png Figure 13i. Modified Bang-Bang Phase Detector A bang-bang phase detector is different from a linear phase detector since the output signals are fixed pulses and they signify if the feedback clocks rising edge is early or late. Those early and late signals are then fed into a charge pump, which tells the VCO (by means of a loop filter) to go faster or to slow down. Simulating this modified version of a phase detector was performed in Simulink. The feedback (reference) signal was delayed compared to the DATA clock. This implies that the phase detector outputs a logic high for the LATE signal, in which it does. M:SJSUEE 227ProjectReport PicturesFigure 13ii- BBPD Test.png Figure 13ii. Bang-Bang Phase Detector Test Results D. Quadrature Clocks Quadrature Clocks are clocks that are separated by 90 degrees. The model to accomplish this was given in figure 11 of the VCO. Testing this with a simple pulse generator input signal provided the plots in figure 14. These plots show four signals that are 90 degrees out of phase with one another. M:SJSUEE 227ProjectReport PicturesFigure 14- Quad Phases.png Figure 14. Quadrate Phases Reading from the top of figure 14 to the bottom, the phases are as follows: 0, 90, 180, and 270 degrees. E. Counter To ensure the entire 360 degrees of phases are covered, as given in the VCO, a counter was implemented. For this simulation, an 8-bit counter was used. This implies that for 360 degrees and an 8-bit counter, each degree represents 1.41 degrees of resolution. The importance of this is related to the unit circle. For a count from 0-255, each 64 counts represents a phase shift of 90 degrees. A simple counter was constructed in Simulink using a just three blocks as shown in figure 15. M:SJSUEE 227ProjectReport PicturesFigure 15- Counter.png Figure 15. Counter Model F. Alpha, Beta, and MUX Values To determine the alpha, beta, and the MUX values, a model was created in Simulink. From section C, an 8-bit counter was created. Of these 8-bits, bits 0-5 represent the alpha bits and bits 6-7 represent the MUX bits. These bits were extracted and then the alpha and the beta values were obtained as mentioned in section A and equation (1). A Simulink model is given in figure 16. M:SJSUEE 227ProjectReport PicturesFigure 16- Alpha Beta Mux.png Figure 16. Alpha, Beta, and MUX Extractor Testing the model in figure 16 revealed an interesting note. This model was taken directly from [3] and when a simple test of this block was performed, the MUX bits appeared to be out of the ordinary. It was expected that the MUX values would range from 0-4 as two bits were extracted, giving a four step ramp. However, the four step ramp ranged from 0-192. This is shown in figure 17. The next section discusses the MUX switching and this is why the issue was noticed. Because of this, this discussion will take place in the next section. M:SJSUEE 227ProjectReport PicturesFigure 17- Alpha Beta Mux Test.png Figure 17. Alpha, Beta, and MUX Test Results G. MUX Model Since a PI requires the use of two different phases simultaneously, a MUX is required to give the proper signals. In Simulink, a MUX was generated using multiport switch components. The model is given in figure 18 below. As there are four inputs, the select line is required to be a value of 1, 2, 3, or 4 in order to properly select the desired line. The select line is driven by the 2-bit MUX value that was obtained in the previous section, F. This implies that the MUX values should be a 1, 2, 3, or 4 value and not the values that are shown in figure 17. The four steps are correct, but further work is need to properly generate the appropriate select lines. Due to the MUX select lines not functioning properly, the final PI PLL design was unable to be properly tested. A solution to this problem is to write a piece of code that reads the MUX line and then determines the proper, 1, 2, 3, or 4 value. M:SJSUEE 227ProjectReport PicturesFigure 18- MUX Model.png Figure 18. MUX Model H. Finall PLL Block and Testing The final design of the complete PLL with the phase interpolator PLL is given in figure 19. As stated in MUX Model section, the MUX line had a critical error that prevented the PLL from being properly simulated. This error was due to the MUX select lines not being of the proper value. If given more time, code would be implemented to resolve this problem or the use of Simulink blocks to generate the proper values for the select lines. M:SJSUEE 227ProjectReport PicturesFigure 19- Final PLL Block.png Figure 19. Final PLL Design with PI For simplicity do to time constraints, a simple test was performed on the final design. Since the MUX select lines are not function properly, a constant value was fed into the select lines to manually pick the phases. When the select line was set to 1 for both, the graph in figure 20 was generated. M:SJSUEE 227ProjectReport PicturesFigure 20- Final PLL Test MUX 11.png Figure 20 PI Output/Feedback Pre Relay Figure 20 shows that the PLL is working to a degree. Unfortunately, it fails to be properly tested. Conclusion PLLs are commonly used devices in a wide range of applications. In this design, a phase interpolator version of a PLL was examined. Although the complete model was successfully constructed in Simulink, the final design was unable to be properly tested. This was due to the malfunction of the MUX select lines that prohibited the simulation to run. A quick work around was implemented, which meant the manual adjustment of the MUX select lines.

Essay on Toni Morrisons Beloved - Character Naming :: Toni Morrison Beloved Essays

Character Naming in Beloved "What's in a name? That which we call a rose By any other word would smell as sweet. So Romeo would, were he not Romeo called, Retain that dear perfection which he owes Without that title. Romeo, doff thy name, And, for thy name, which is no part of thee, Take all myself." hakespeare, Romeo and Juliet, II.ii Shakespeare's Juliet tells us that names are unimportant - inconsequential, in fact. A name is merely a convenient string of sounds that denotes an individual, but it has no meaning. But this is clearly not true. Would Romeo and Juliet be the same play if its star-crossed lovers were called Robert and Jennifer? Of course not. The names of characters serve to identify them as members of a certain culture and help to cement their identities. A name may be an arbitrary string of sounds, but it carries much more weight than that. In Beloved, Toni Morrison demonstrates a clear understanding of this fact. Her choices of character names assist in firmly establishing the world of the book. Toni Morrison was born with the name Chloe Anthony Wofford. She changed her first name to Toni upon entering college - traditionally, a time looked upon as one of great significance in a young person's life. From this, we can infer that Morrison appreciates the power of a changed name to confer a new identity. There are two characters whose names change during the novel: Jenny Whitlow becomes Baby Suggs, and Joshua becomes Stamp Paid. In both of these cases, the character is abandoning the name under which they lived as a slave for a new, free name. Whitlow is the last name of Jenny's original master (142), and we learn that she takes the name Baby Suggs because her husband called her Baby. What she is known as by the people closest to her is more important than what the white community wishes to call her. The name Sethe is also interesting. This name could be interpreted as a feminine version of the Jewish name Seth, used in the fourth and fifth chapters of Genesis as the name of the third son of Adam and Eve, after Cain and Abel.

Personality Analysis of Anthony Kiedis

Samantha Selody Professor Dana Nelson Theories of Personality 10 October 2012 Personality Analysis of Anthony Kiedis Anthony Kiedis was often considered a â€Å"trouble maker† from a young age. By the third grade, he had developed a real resentment toward the school administration and teachers because if anything went wrong, he would be routinely pulled out of class and considered to be the cause of the problem. Because Anthony did not have any good male role models early on in his life, he developed a problem with authority figures and had no one to rein in any antisocial behavior (Kiedis, 2004, p. 9). Anthony moved to Hollywood, California to live with his father in 1974 at the age of twelve. Anthony’s father, John Michael Kiedis (a. k. a. Blackie Dammett) promoted a highly indulgent-permissive style of parenting. McAdams (2009) describes this particular practice of parenting as having few high standards set for behavior but are highly responsive to children (p. 82). Although Anthony did do well in school and with his work, he was not expected to and was often distracted from his school work and left to fend for himself when it came to food and actually arriving at school.Anthony’s father did not provide a good social learning environment for him. His father allowed him to smoke marijuana and do other illicit drugs at the young age of 12 (Kiedis, 2004, p. 26). Anthony was also exposed to a variety of sexual encounters that most would find inappropriate for a 12 year old to experience. Anthony’s father often exposed him to the Hollywood night club scene where he was encouraged to drink and stay up extremely late with his father and other adults.From these experiences, Anthony learned from his social surroundings that drug use, partying, and alcohol were a social norm and something that was acceptable to do. This ultimately set him up for severe drug problems that occurred and lasted for a considerable amount of time during his adole scent and adult life. From a young age, it was clear that Anthony exhibited a high level of openness to experience. McAdams defines those who are high on openness to xperience as, â€Å"original, imaginative, creative, complex, curious, daring, independent, untraditional, liberal, and having broad interests (p. 185). This trait was most likely reinforced by his father who would also be high on this scale. One of Anthony’s favorite assignments in school was writing. His English teacher noticed that he had a gift for writing and encouraged him to continue to write. Anthony describes this as â€Å"a bell that wouldn’t stop ringing for the rest of his life† (Kiedis, 2004, p. 38). Anthony was also a big risk taker.He often devised schemes with his friends to obtain alcohol from homeless people. However, he eventually realized that he could just steal it himself, so he began to do just that. Anthony stole basically anything he wanted, whenever he wanted and was never caught or punished for it. This positive reinforcement fed in to his degree of openness to new experiences. Anthony was always seeking a thrill, and by observing his father, he recognized that he could get excitement by doing drugs, drinking, having sex and doing outrageous activities.It is important to note that all of these things occurred early in his life and throughout his adolescence. His actions were validated by his father and imitated by his friends who thought that he was having a great time. However, although he frequently abused drugs, Kiedis maintained his grades in school. Kiedis explains that, â€Å"I smoked a ton of pot, took pills, and drank on the weekends. But it never got out of control†¦It was important to me to be the straight-A student.In a way, I was a rebel by getting good grades, because most of the stoners and the druggies were getting no grades. I didn’t want to be like them†¦I wanted to be the best at whatever it was that was in front of me† (p. 78). This attitude was a driving factor is Anthony’s life. He wanted to be the best at whatever he did, whether it was school, performing, drinking, or doing drugs. This attitude also fed in to his level of openness because not only was he willing to try new things, he wanted to be the best at whatever he tried, which propelled him to even more experiences.

The Purpose of Prisons Essay - 546 Words

The Purpose of Prisons In prisons today, rehabilitation, deterrence, incapacitation, and retribution are all elements that provide a justice to society. Prisons effectively do their part in seeing that one if not more of these elements are met and successfully done. If it were not for these elements, than what would a prison be good for? It is highly debated upon whether or not these elements are done properly. It is a fact that these are and a fact that throughout the remainder of time these will be a successful part of prison life. When a prisoner enters a prison, it is presumed he is guilty of the crime he was charged with. If this is true, the prison has an obligation to do something about this criminal. They are not going†¦show more content†¦This is proof that the prisons are doing their job in rehabilitating prisoners. Prisons not only rehabilitate, but they also deter people from going to prison. The fear of going to prison is a great deterrence for a perspective criminal. Hard li fe styles along with loss of freedom tend to push the criminal away from the chance of being incarcerated. Numbers show that there are fewer rapes, and fewer murders, each year, all an obvious product of prison deterrence. After all, if a person has a friend who just got out of jail, and hears all of the war stories, that person would surely not want to go to prison and end up like his friend. By making life in prison hard, the prison is doing a great job in getting the word out. Prison is no joke! They are doing their job in deterring criminals from wanting to enter the gates of hell. For those people who are not deterred, they are punished accordingly. They are removed from the street and placed in a tiny cell, usually with two people in it. There time for freedom is long gone, and they live the life of prisoners under prison law. The prison sees to it that no longer will the criminal be able to rein terror on the community because they are locked behind bars. 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